There have been many years since the 1998 announcement of\ncarbon nanotube transistors. The hope\nhas been for the semiconductor industry to create a means of producing a carbon\nnanotube computer. First, why is there a\nneed to replace the current semiconductor manufacturing process? The ability to reduce the minimum feature\nsize dimension by 30% has been occurring on re regular basis of 18 to 24 months\nfor decades. A 30% reduction results in\nthe dimension shrinking to 70% of the previous size. With both length and width shrinking 70%, the\nare required is 49% of the previous area. \nConsequently, twice as many features can be fabricated in the same area\nas previously possible. <\/p>\n\n\n\n
The imaging process (lithography) is limited by the minimum\nfeature size possible from the source that produces the images. Lithography tools produce images that have\nmuch greater precision than the best photographic lenses available today. In addition to the high precision of the\nlithography equipment, there are a number of optical tweaks that can further\nrefine the image quality. There is a\nphysical limit on how far engineering can push the physical limits of imaging. Optical lithography went from visible\nwavelength to ultraviolet wavelengths (shorter wavelengths) and then to even\nshorter wavelengths. The current latest\nlithography tools employ a wavelength of 13.5 nanometers (nm). This is being used to produce images that\nhave one of their dimensions under 10nm. \n(If interested in further reading on the latest processes, please see\nreference #1.)<\/p>\n\n\n\n
There are challenges as the dimensions shrink. Multiple process steps require higher\nprecision equipment and more costly steps. \nAdditional manufacturing steps increase the amount of time required to\nmanufacture the semiconductors. Additional\nsteps also provided opportunities for decreasing the yields of the final\ndevices. All of this raises cost.<\/p>\n\n\n\n
As dimensions shrink, there is potential for unwanted\nelectrical characteristics to become present. \nThis degrades the performance of the devices. As the size shrinks and more electronics\ncircuitry is incorporated, the total distance the signals must travel in a\ndevice increases. There are some\nestimates that 50% of the power for the leading edge devices is used to move\nthe electrical signals through the circuitry. \n<\/p>\n\n\n\n
Why does the industry continue on as it has in the\npast? Currently, there is nothing else\nthat can produce billions of connected transistors every second.<\/p>\n\n\n\n
According to a C&EN article (Ref. 2), DARPA is\ninterested in carbon nanotube circuits. There\nare a number of methods to apply the nanotubes into circuitry that will provide\nbetter performance with lower power consumption. One of the challenges mentioned in the\narticle is the caution needed in handling some of the exotic materials within\nthe clean space required for semiconductor manufacturing. Many materials can have very detrimental\nimpacts of the production process. <\/p>\n\n\n\n
Back in the 1990s, the Advanced Technology Development\nFacility of SEMATECH instituted a process where they could annually handle as\nmany as 40 different exotic and potentially process disastrous materials\nwithout danger of contamination.<\/p>\n\n\n\n
The process for producing the carbon nanotubes requires a\nseed for growth of the tubes. Typically,\nthe seed material is one that should not be permitted to be the clean environment\nof semiconductor manufacturing. It can\nbe done correctly and provide the safety controls required to manufacture the semiconductors.<\/p>\n\n\n\n
Part 2 will cover the possible types of transistor designs\nunder consideration and some of the issues in implementing them into existing\nmanufacturing.<\/p>\n\n\n\n
References:<\/p>\n\n\n\n
There have been many years since the 1998 announcement of carbon nanotube transistors. The hope has been for the semiconductor industry to create a means of producing a [..]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[9,10],"tags":[],"class_list":["post-333","post","type-post","status-publish","format-standard","hentry","category-nano","category-semiconductor-technology"],"_links":{"self":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts\/333","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=333"}],"version-history":[{"count":1,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts\/333\/revisions"}],"predecessor-version":[{"id":334,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts\/333\/revisions\/334"}],"wp:attachment":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=333"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=333"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=333"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}