{"id":336,"date":"2019-06-30T11:11:44","date_gmt":"2019-06-30T16:11:44","guid":{"rendered":"http:\/\/www.nano-blog.com\/?p=336"},"modified":"2022-09-02T12:57:41","modified_gmt":"2022-09-02T17:57:41","slug":"a-coming-disruption-in-technology-part-2","status":"publish","type":"post","link":"http:\/\/www.nano-blog.com\/?p=336","title":{"rendered":"A coming disruption in technology? Part 2"},"content":{"rendered":"\n

The design of the semiconductor circuit components has been\nevolving as the feature size shrinks. \nThe semiconductor industry has been able to develop new designs as older\ntechniques become restrictive due to various material properties.  This blog is a short review of the history of\ndevelopment of device structures with some thoughts on the coming changes.  There were many different types of\ntransistors during the 1950s, 1960s, and into the 1970s.  These can be found in many places on-line,\nincluding Wikipedia [Ref. 1].<\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n

The field effect transistor (FET) has been a staple of semiconductor manufacturing for years.\u00a0 The majority of the devices produced through the 2000s were complementary metal-oxide-semiconductors (CMOS).\u00a0 The picture below, from reference #2 shows the components of the FET.<\/p>\n\n\n\n

The manufacture of FETs are directly ono the silicon\nwafers.  The gate electrode is the control\nfor the flow of the charges, either electrons or holes.  The structure is structured with planar\nlayers, which gives rise to the term \u201cplanar gate\u201d.  As the size of the semiconductor components,\nthe dimensions became smaller.  The\nshrinkage of the gate length increased the switching speed with the result\nfaster electronics.  Problems began to\narise as the gate length shrunk toward 20nm. \nThe current could flow without any control by the gate electrode.  <\/p>\n\n\n\n

The issue of not having enough surface area to control the FET was addressed with the development of the FinFET.\u00a0 The picture below is from reference #3.\u00a0 The gate material is vertical and provides more volume for controlling the flow of the charge.\u00a0 The \u201csource\u201d and \u201cdrain\u201d are also vertical (fins) that provide a better control that operates at a lower voltage, which also provides better performance.\u00a0 Unfortunately, the design is more complex and challenging to produce.\u00a0 Semiconductor manufacturing has kept up with these challenges, but \u2026..\u00a0 <\/p>\n\n\n\n

\"\"
F<\/strong><\/figcaption><\/figure><\/div>\n\n\n\n

With the current view of the future of production, FinFET are starting to reach their limit.\u00a0 So, a different solution needs to be developed.\u00a0 There are some thoughts about increasing the \u201cfins\u201d to cover more contact area.\u00a0 This is shown below as the Gate-All-Around FET [Ref. 4].\u00a0 Others are looking at different designs.\u00a0 The Multi-bridge Channel FET was identified in the early 2000s, but manufacturing technology was not available.\u00a0 <\/p>\n\n\n\n

\"\"
Coming soon?<\/strong><\/figcaption><\/figure><\/div>\n\n\n\n

The development of the GAAFET was led by IBM.  Samsung has move beyond the collaboration to\nthe MBCFET, which it contends will be in production for the 3nm node.  <\/p>\n\n\n\n

There are challenges to gate-all-around designs.  There is only modest improvement over FinFets\nat 5nm.  The manufacturing technology is\nchallenging [Ref. 6] with tighter manufacturing requirements due to greater\ncomplexity.  The current version of the\ndevices requires a silicon, silicon-germanium, and silicon super lattice\nstack.  More details of the process is\navailable in reference 6.  The projection\nis for the introduction on the GaaFET at 3nm.  \n<\/p>\n\n\n\n

Historically, each succeeding node brings with it move\ntransistors per unit area with lower power and higher performance at a lower\ncost per transistor.   Due to the greater\nchallenges in producing the smaller and smaller transistors, that fact is no\nlonger true.  The question I s not\nwhether or not the technology will continue to advance, but how will the\ntechnology transform to continue to provide more capable devices.<\/p>\n\n\n\n

References:<\/strong><\/p>\n\n\n\n

  1. https:\/\/en.wikipedia.org\/wiki\/Transistor<\/a><\/li>
  2. Chapter 2: Nanotechnology in Electronics, Larry\nLarson et al, Nanotechnology for Sustainable Manufacturing. Pp. 17-35. CRC\nPress. David Rickerby editor.  2016.  ISBN13: 978-1-4822-1483-3 <\/li>
  3. https:\/\/blog.lamresearch.com\/tech-brief-finfet-fundamentals\/<\/a><\/li>
  4. https:\/\/www.pcgamesn.com\/samsung\/3nm-gaa-beat-tsmc<\/a>\n<\/li>
  5. https:\/\/wccftech.com\/samsung-announces-3nm-mbcfet-process-5nm-production-in-2020\/<\/a>\n<\/li>
  6. https:\/\/semiengineering.com\/5nm-vs-3nm\/<\/a>\n<\/li><\/ol>\n","protected":false},"excerpt":{"rendered":"

    The design of the semiconductor circuit components has been evolving as the feature size shrinks.  The semiconductor industry has been able to develop new designs as older techniques [..]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[9,10],"tags":[],"class_list":["post-336","post","type-post","status-publish","format-standard","hentry","category-nano","category-semiconductor-technology"],"_links":{"self":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts\/336","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=336"}],"version-history":[{"count":1,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts\/336\/revisions"}],"predecessor-version":[{"id":340,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts\/336\/revisions\/340"}],"wp:attachment":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=336"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=336"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=336"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}