In our June 30 blog, we covered Part 2 of an upcoming\ntechnology disruption. This blog is covering\nmaterial from the IEEE Spectrum magazine [Ref. 1] on a Carbon Nanotube microprocessor. A more detailed article is available from\nNature [Ref. 2]. CNT transistors have\nbeen around for more than 10 years. There\nhave even been some processors assembled into extremely simple \u201ccomputers\u201d. This device contains nearly 15,000\ntransistors. It has the ability to say \u201cHello\u201d,\nwhich is the traditional test of a functioning computer. Current microprocessors contain billions of\ntransistors, so there is still a long way to go, but it is a start. <\/p>\n\n\n\n
Key facts of the development created by a team from MIT and\nAnalog Devices include it is a fully programmable 16-bit carbon nanotube\nmicroprocessor. It is based on the\nRISC-V instruction set and can work with both 16-bit and 32-bit instructions. In order to accomplish this, there were three\nproblems that needed to be overcome. <\/p>\n\n\n\n
In our opinion, the most challenging was the fact that there\nis no process that will create only semiconducting CNTs. There is always a mix of metallic with the\nsemiconducting CNTs. There are\nindications that today\u2019s best processes for semiconducting CNTs can produce\nfour 9s semiconducting purity but not the eight or nine 9s required for a\nrobust manufacturing process. The issue\nwith the impurity is an increase in signal noise. <\/p>\n\n\n\n
As with many breakthroughs, the solution is different from\ndeveloping additional ways of increasing the semiconducting CNT purity. The researchers worked with various circuit\ndesigns to analyze the capabilities of the designs. What was found is that there is a pattern of\nresults that suggested certain combinations of logic gates were better in\nsignificantly reducing the noise. The\npower waste issue turned out to be minor compared to the noise issue. With this information, they developed a set\nof design rules that permits large scale integration of CNTs with readily\navailable purity.<\/p>\n\n\n\n
The issue how to create the circuitry was the first one\nsolved to get to the important development above. Typically, CNT transistors are created by\nspreading a solution with CNTs uniformly across the surface of a wafer. The issue they had is that there are aggregates\nor clumps of CNTs bundled on the surface. \nObviously, this is unacceptable due to the clumps being unable to form\ntransistors. The solution was to use the\nfact that single CNTs are held to the surface by van de Waals forces and\nbundles of CNTs are not; so, it is possible to remove the bundles. <\/p>\n\n\n\n
The third challenge is that for CMOS logic, both NMOS and\nPMOS transistors are required. It is not practical to try to dope individual structures\nto provide the desired N or P characteristic. \nThe researchers employed a dielectric oxide to either add or subtract\nelectrons. Using atomic layer deposition\n(ALD), they were able to deposit an oxide with the desired properties one\natomic layer at a time. By selecting the\nproper materials, the researchers were able to reliably create PMOS and NMOS\ndevices together. This process is a low\ntemperature process that permits building layers of transistors between levels\nof interconnects.<\/p>\n\n\n\n
The interesting concept provided in developing the CNT microprocessor\nis that the processes employed are currently employed in semiconductor manufacturing. The development of this type of concept into\na full, high volume device does not require the development of a new industry\nwith new tooling requirements. It is\npossible that as the techniques evolve, current semiconductor manufacturing companies\ncould evolve the processes and not have a major retooling effort. This fact could encourage the hastening of\nacceptance of CNT transistors. It will be\ninteresting to observe the progress over the next few years.<\/p>\n\n\n\n
References:<\/strong><\/p>\n\n\n\n In our June 30 blog, we covered Part 2 of an upcoming technology disruption. This blog is covering material from the IEEE Spectrum magazine [Ref. 1] on a [..]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[9],"tags":[],"class_list":["post-348","post","type-post","status-publish","format-standard","hentry","category-nano"],"_links":{"self":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts\/348","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=348"}],"version-history":[{"count":1,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts\/348\/revisions"}],"predecessor-version":[{"id":349,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=\/wp\/v2\/posts\/348\/revisions\/349"}],"wp:attachment":[{"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=348"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=348"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.nano-blog.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=348"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}