Author Archives: Walt

Moore’s Law is quoted in many different forms.  Basically, area density is a primary focus.  If the difference between generations in a 30% reduction in dimensions, then the area for a transistor (70% by 70%) is reduced by almost 50% … Continue reading →

There has been more information in the press about the coming 3nm generation of semiconductors.  [Note: I am on the semiconductor roadmap Litho subcommittee. Only information in the public domain will be covered in any of these blogs.) As pointed … Continue reading →

As 2022 begins, predicting (guessing) where technology will go is almost always wrong.  This is an opportunity to highlight some of the developments that that appear possible to occur. Nanomaterials: Nanomaterials have been around for more than a couple of … Continue reading →

We already reported on the development of two-dimensional nano-sheet transistors and other two-dimensional materials.  One of the challenges that has been previously mentioned is the fact that we do not know the material properties of “pure” materials.  Current technology provides … Continue reading →

Previously, we have covered the challenges of experiments and the need for reproducibility.  Recently, there has been an additional occurrence that merits discussion.  There has been a study where roughly 100 peer reviewed articles that were published in respectable journals … Continue reading →

In previous blogs, two dimensional semiconductors have been discussed.  Work at Singapore University of Technology and Design has developed a different approach to solving the issues of very small transistors that will be required for future generations of semiconductors [Ref. … Continue reading →

With the emphasis on nanotechnologies and the emphasis on two-dimensional materials, other areas that are pushing boundaries are often overlooked.  A recent article [Ref. 1] summarizes work done at King’s College London on relieving pain.  Their treatment employs a ultra-low … Continue reading →

Last month, this blog covered some of the challenges of continually shrinking semiconductor geometries and the related difficulties with traditional transistor designs.  This month’s blog explores transistor geometry.  In May 2021, IBM announced a 2nm nanosheet semiconductor technology. [Ref. 1]  … Continue reading →

As semiconductor manufacturing continues the dimensional shrinking process, novel ideas are required to achieve the ability to continue shrinking the dimensions while increasing the performance.  There are some thoughts that this potion of the Moore’s law curve will provide some … Continue reading →