The use of “nano” has become commonplace. Projections are made about creating individual items/molecules/devices at the nano-scale. There are examples of nano clocks, vehicles, etc. Given enough effort, funding, and time, it is possible to create a large variety of nano-things. Making one is not the problem. It is manufacturing them in volume quickly and efficiently.
Today’s semiconductors may contain over one billion transistors. The devices are made on silicon wafers that can be as large as 450 mm (about 18”). The devices themselves are millimeters in dimensions, which provides the ability to create thousands of devices on a single wafer. The processing of the wafers is normally done in lots of multiple wafers to efficiently use the very expensive equipment required for making semiconductors. As the dimensions of the transistors have been decreasing, the cost of the equipment to build a semiconductor manufacturing fabrication facility (also known as a Fab) is increasing and will be in the $10s of billions. The changes in the size of features has been following a observed rule, called Moore’s Law, that projects a reduction in dimensions of 70% over a period of 18 to 24 months. (70% in length and 70% in width yields a 50% reduction in area or a doubling in density.) The current and next generation of equipment to manufacture the smaller sizes are requiring equipment that is larger and larger. The tools used for creating the images on the wafers are increasingly complex and becoming much larger. In addition to the size shrinkage, more complex circuitry requires more supporting connections, which increases the number of levels each device has. Additional levels require more equipment to be able to manufacture the devices. It is to the point that the new equipment does not fit into many existing facilities. Thus, new facilities need to be constructed.
What does that have to do with nano devices? The nano devices need to be manufactured somehow. Currently available 3D printing technology has a limit of about 25 micrometers or about 0.001 inch, and it is not very fast. If we consider the current state of semiconductor production, tolerances are a fraction of the desired feature. If one is considering 14 nm features, the placement of related features needs to be a small fraction of that dimensions. How is that achieved. There are many ways, but consider two. The creation of a fiducial mark on the silicon substrate can be employed for alignment, but the ability to register to the fiducial marks must be very accurate. It is possible to also register from a carefully created edge on the material, which is easier to find than the fiducial mark. This appears to be a couple of good means for establishing relative positioning. There is one issue. If the 14 nm features are considered, the tolerance is going to be less than 3 nm. How does one create material with an edge or a fiducial mark that is accurate to 3 nm? It is not easy.
In order to manufacture something in quantities, it is necessary to be able to measure the characteristics of the object to at least an order of magnitude smaller than the dimension being measured. If the 3 nm dimension is considered, an order of magnitude smaller means measuring atoms.
So the Key Challenge is the development of tools that can quickly and accurately measure dimensions that are very small with nanometer and sub-nanometer precision.