Is Nano too large?

Are we starting to see device developments at the atomic level?  During 2017, there have been many stories on graphene and other two-dimensional materials.  Various companies have started developing production capabilities.  Yes, graphene and similar material are only one atom thick.  Does this make them at the atomic level?  In one dimension, the answer is yes.  The other dimensions are much larger.  What we are starting to see is the development of devices that combine different two-dimensional materials to produce interesting devices.

A team consisting of University of Texas – Austin researchers collaborating with Peking University researchers has develop a very thin and very dense memory. [Reference 1]  Previously, semiconductor fabrication has separate areas on a device for computing circuity and the memory storage.  The researchers have called the devices “atomristors” to emphasize their work should improve on the capabilities of memristors.  Their technical paper is available through reference #2.  The increase in density is due to the application of multiple two-dimensional materials.  The entire memory cell is less than 2 nanometers thick.  While they did not mention this fact in the general publications, these devices should be faster and require reduced power for comparable semiconductor devices performing the same functions.

Memristors are not disappearing.  They are a type of Re(sistive)RAM, which was projected to replace NAND.  Memristors work by changing the resistance of the material.  The use of the memristors is different in that the change in the material in not necessarily binary but can be considered analog.  Of course, all the semiconductors are based upon on and off states.  So, to fully use the capabilities it requires something that is more analog based.  As mentioned last year, there are solid-state vacuum tubes, which are analog.  Maybe there is some interesting possibilities that can employ both types of devices.

As the speed of calculations increase, the issue becomes the time lag in getting signals across the semiconductor device.  It might seem strange that there is a signal lag across the such a small dimension but that is actually the case.  Researchers are looking at using optical fiber to transmit the signals.  This creates other complexity for the circuitry in converting signals on both ends of the transmissions.  As semiconductors dimensions continue to shrink, the size of key features will be well below 10 nanometer.  There are issues with making these small features in mass production, the size is below any existing light source for lithography to create the patterns,  The semiconductor industry has been creative in the development of sources that produce features well below the Rayleigh limit (wavelength/Smilie: 8).

Current tools use immersion lithography to create the majority of very fine images employed today.  This process requires the use of multiple masks per individual layer.  This is an expensive process.  The application of EUV (13.5nm) has the potential for smaller features.  It is anticipated the EUV will be coming into semiconductor manufacturing in a major way.  The challenge is the production of features that are less than 5nm.  If the images need to have a 10% range of feature sizes, that means controlling the features to 0.5nm (or 5 Angstroms).

We will be seeing more experimental tools that can measure/image features with accuracies that are much less than 1nm.  It should be an interesting year.

 

References

  1. https://news.utexas.edu/2018/01/17/ultra-thin-memory-storage-device-for-more-powerful-computing
  2. http://pubs.acs.org/doi/10.1021/acs.nanolett.7b04342

About Walt

I have been involved in various aspects of nanotechnology since the late 1970s. My interest in promoting nano-safety began in 2006 and produced a white paper in 2007 explaining the four pillars of nano-safety. I am a technology futurist and is currently focused on nanoelectronics, single digit nanomaterials, and 3D printing at the nanoscale. My experience includes three startups, two of which I founded, 13 years at SEMATECH, where I was a Senior Fellow of the technical staff when I left, and 12 years at General Electric with nine of them on corporate staff. I have a Ph.D. from the University of Texas at Austin, an MBA from James Madison University, and a B.S. in Physics from the Illinois Institute of Technology.

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