Semiconductor Nanotechnology

What is the state of nanotechnology in creating semiconductors?  As the size of the individual semiconductor components shrink, the current material employed starts to create concerns.  Projections have been made for incorporating nanomaterials, like conductive carbon nanotubes, for interconnects between levels of the semiconductor circuits.

Note to readers about semiconductor manufacturing.  There are many levels (layers) in a single semiconductor.  The transistors are the basic individual device and consists of a combination of materials that permit a specific charge to change its state to either permit electron flow or not.  To interconnect one transistor to another requires some conductive material.  With billions of transistors on a single integrated circuit, there are many levels on interconnects required.  To provide the conductive path for the current required connecting one level to another level, possibly tens of layers removed.  [Ref. #1]  Currently materials, like tungsten, are employed.

The issue with employing carbon nanotubes is that conducting nanotubes would be required to fill each of the desired connects.  Current carbon nanotube manufacturing technology can not produce only conducting nanotubes with a yield of parts per billion.  Even if the desired yield could be produced, how would the nanotube be placed in the correct location?

There is work being done on using graphene with germanium [Ref. #2].  It appears to be able to form smooth ribbons with curved surfaces.

Directed self-assembly (DSA) of interconnects is being developed.  The critical issues are both placement and defect identification.  There should be some development along these lines in the next two years.

Another approach is to employ semiconducting nanowires.  [Ref. #3]  These structure provide unique characteristics of the materials.  One of the challenges in using these structures is the requirement for placement.  Based on some of the work currently being done, it is possible to have these structures placed on a regular pattern or grid.  Employing the interconnecting levels as currently being done could provide a possible means to go forward.

Currently, the design of transistors is moving to have more of a vertical component.  Employing vertical nanowires (nanotubes) could be a further step in this direction.  It would be possible to mass produce the transistors as done today, which assumes the yield of the correct type will be possible.  One large problem is still placement of the devices.  I have seen 100nm vertical nanowire grids created.  The possibility exists of getting that values down to 10nm.  Even at 10nm, the long term needs may not be satisfied.

Conclusions:  Nanomaterials are being investigated for applications in semiconductors.  The work that is being done has not yet provided solutions for the high volume production required for the existing state-of-the-are devices.

The above commentary is focused on semiconductor circuitry.  There are efforts addressing the solar energy arena that are incorporating nanotechnology and improving the performance of the photovoltaic cells.  There is additional efforts in quantum computing that are in their infancy.  It will be interesting to observe what direction these efforts and how they can be commercialized.

References:

  1. https://electroiq.com/2011/03/nanotechnology-for-semiconductors/
  2. http://www.advancedmp.com/nanotechnology-semiconductors/
  3. http://www.annexpublishers.co/articles/JMSN/5202-The-Role-of-Nanotechnology-in-Semiconductor-Industry-Review-Article.pdf

About Walt

I have been involved in various aspects of nanotechnology since the late 1970s. My interest in promoting nano-safety began in 2006 and produced a white paper in 2007 explaining the four pillars of nano-safety. I am a technology futurist and is currently focused on nanoelectronics, single digit nanomaterials, and 3D printing at the nanoscale. My experience includes three startups, two of which I founded, 13 years at SEMATECH, where I was a Senior Fellow of the technical staff when I left, and 12 years at General Electric with nine of them on corporate staff. I have a Ph.D. from the University of Texas at Austin, an MBA from James Madison University, and a B.S. in Physics from the Illinois Institute of Technology.

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