Move over “Nano”, “Pico” is coming.

Nothing remains on top (or at the bottom) forever.  “Pico” is three orders of magnitude smaller than “nano”.  A rule-of-thumb is that to be able to manufacture or produce something, one must be able to measure to at least an order of magnitude smaller and more likely two orders-of-magnitude smaller.  Why?  In order to mass manufacture something, one needs to be able to make it so that there is consistency from one item to another.  If pieces go together, they need to have a tolerance so that the fit is acceptable. 

There is a story that circulated during the early application of robots that the robots could not do what assembling humans were doing.  It turned out that the parts being assembled had a slight variation in the centering of the pieces.  The human worker could make an adjustment, but the robot could not make that adjustment.  The tolerances were changed and the robots were “happy” and assembled the parts.  The tolerances had to be made smaller for the automated assembly to function properly. 

So what does that have to do with “pico”?  Please bear with me on getting to the point why “pico” is needed.  As the reader is probably aware, the semiconductor industry has been steadily decreasing the size of the size of the circuitry in the semiconductors.  The reduction in the minimum feature size dimension has been reducing at of rate of 0.7 every roughly 18 months.  (A 0.7 reduction in dimension results in an approximately 50% area reduction.)  This observation was first quantified by Gordon Moore of Intel and has become known as Moore’s Law.  The current “next” generation being developed for semiconductors is below 10nm. 

Semiconductor manufacturing consists of processing many 10s of layers, each layer contains different portions of the final circuitry.  The material on each of the layers is modified by various process that create the desired features.  The process involves coating a material, exposing the desired pattern, and then removing or adding specific materials. 

The features for the semiconductor are produced by illuminating a wafer with light that is modified by an imaging mask.  The mask contains the features that will produce the desired images.  The projection illuminates a resist to create a pattern that can be etched to remove the unwanted portion of the surface.  Typically, the mask has features at a magnification of the final image.  The optical system reduces the image to create the desired feature size. 

Roughly, the minimum “achievable” image spot definition produced by a light source is defined by the wavelength.  The wave nature of length produces diffraction patterns, which have alternating rings of light and dark.  Lord Rayleigh defined the minimum separation at which it is possible to identify separate points is when the center of the one spot falls into the first dark ring of the other spot.  The actual separation also includes a relationship to the diffraction limit of the angular illumination from the lens system.  In this discussion, we will use the wavelength divided by 4.  (This would require extremely good optics.)  The current semiconductor tools in widespread production employ 193nm wavelength sources.  With that assumption, it would appear that spots of 50nm could be produced.  But, there are other influences that degrade the images. A key factor is aberrations or distortions introduced by the lenses.  Another issue is that the images produced need to have vertical sidewalls and not the slope of two overlapping images.  Add to that the fact that resists do not produce smooth patterns at the nanoscale size.  The molecules of the resist cause roughness.  Then the actual lens system is also limited by the index of refraction of the lens material (for transmissive systems) and the numerical aperture, which is a function of the focus angle of the lens system.  The list of imperfections that degrade the final image.

How do we produce such small feature as are being done today?  There are many factors.  The application of immersion techniques to the 193nm systems has further reduced the feature size possible.  The development and application of mathematical techniques that evaluate the interference of light provides the ability to actually use features on the mask to prevent portions of adjacent features from being imaged.  (For a more in-depth understanding of these techniques, publications by Chris Mack are recommended.  See reference 1.)  These imaging systems, known as Lithography systems, are very large and quite expensive.  There are many engineering innovations that have become part of the existing Lithography systems.

The optics are the key to successful imaging.  Surface variations in the lens cause defects in the image on the surface.  The surface smoothness of a lens from the theoretical design is measured and the resultant number is called the Root Mean Squared (RMS) error.  RMS is basically an estimation of the deviation from the perfect design.  The current state-of-the-art for high resolution camera lenses is roughly 200nm RMS. 

As presented in the Keynote Session presentation at the Advanced Lithography Conference, the current RMS for the latest Lithography systems in production is less than 1nm.  In this presentation, it was stated that the value for the coming image sizes requires the Lithography systems’ RMS to be 50pm.  That is picometers.  One picometer is one thousandth of a nanometer.  [Ref. 2]  This talk referenced a slide from Winfried Kaiser that showed the equivalent of 50pm corresponds to variations across the length of Germany, across 850 Km, would need to be less than 100 micrometers. 

As the feature sizes continue to shrink, the variations in properties will be in the picometer range.  It will probably start out as a decimal point and a nanometer reference.  Nanometers were first referred to as micrometers with a decimal point before the numbers.  “Pico” is coming to nanotechnology.


  1. Chris Mack has various explanations on optical techniques available at
  2. Bernd Geh, EUVL – the natural evolution of optical microlithography, Advanced Lithography 2019, Conference 10957, Extreme Ultraviolet Lithography, Keynote Session, February 2019, San Jose, California. 

About Walt

I have been involved in various aspects of nanotechnology since the late 1970s. My interest in promoting nano-safety began in 2006 and produced a white paper in 2007 explaining the four pillars of nano-safety. I am a technology futurist and is currently focused on nanoelectronics, single digit nanomaterials, and 3D printing at the nanoscale. My experience includes three startups, two of which I founded, 13 years at SEMATECH, where I was a Senior Fellow of the technical staff when I left, and 12 years at General Electric with nine of them on corporate staff. I have a Ph.D. from the University of Texas at Austin, an MBA from James Madison University, and a B.S. in Physics from the Illinois Institute of Technology.

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