Nanotechnology is getting interesting

In our June 30 blog, we covered Part 2 of an upcoming technology disruption.  This blog is covering material from the IEEE Spectrum magazine [Ref. 1] on a Carbon Nanotube microprocessor.  A more detailed article is available from Nature [Ref. 2].  CNT transistors have been around for more than 10 years.  There have even been some processors assembled into extremely simple “computers”.  This device contains nearly 15,000 transistors.  It has the ability to say “Hello”, which is the traditional test of a functioning computer.  Current microprocessors contain billions of transistors, so there is still a long way to go, but it is a start. 

Key facts of the development created by a team from MIT and Analog Devices include it is a fully programmable 16-bit carbon nanotube microprocessor.  It is based on the RISC-V instruction set and can work with both 16-bit and 32-bit instructions.  In order to accomplish this, there were three problems that needed to be overcome. 

In our opinion, the most challenging was the fact that there is no process that will create only semiconducting CNTs.  There is always a mix of metallic with the semiconducting CNTs.  There are indications that today’s best processes for semiconducting CNTs can produce four 9s semiconducting purity but not the eight or nine 9s required for a robust manufacturing process.  The issue with the impurity is an increase in signal noise. 

As with many breakthroughs, the solution is different from developing additional ways of increasing the semiconducting CNT purity.  The researchers worked with various circuit designs to analyze the capabilities of the designs.  What was found is that there is a pattern of results that suggested certain combinations of logic gates were better in significantly reducing the noise.  The power waste issue turned out to be minor compared to the noise issue.  With this information, they developed a set of design rules that permits large scale integration of CNTs with readily available purity.

The issue how to create the circuitry was the first one solved to get to the important development above.  Typically, CNT transistors are created by spreading a solution with CNTs uniformly across the surface of a wafer.  The issue they had is that there are aggregates or clumps of CNTs bundled on the surface.  Obviously, this is unacceptable due to the clumps being unable to form transistors.  The solution was to use the fact that single CNTs are held to the surface by van de Waals forces and bundles of CNTs are not; so, it is possible to remove the bundles. 

The third challenge is that for CMOS logic, both NMOS and PMOS transistors are required.   It is not practical to try to dope individual structures to provide the desired N or P characteristic.  The researchers employed a dielectric oxide to either add or subtract electrons.  Using atomic layer deposition (ALD), they were able to deposit an oxide with the desired properties one atomic layer at a time.  By selecting the proper materials, the researchers were able to reliably create PMOS and NMOS devices together.  This process is a low temperature process that permits building layers of transistors between levels of interconnects.

The interesting concept provided in developing the CNT microprocessor is that the processes employed are currently employed in semiconductor manufacturing.  The development of this type of concept into a full, high volume device does not require the development of a new industry with new tooling requirements.  It is possible that as the techniques evolve, current semiconductor manufacturing companies could evolve the processes and not have a major retooling effort.  This fact could encourage the hastening of acceptance of CNT transistors.  It will be interesting to observe the progress over the next few years.



About Walt

I have been involved in various aspects of nanotechnology since the late 1970s. My interest in promoting nano-safety began in 2006 and produced a white paper in 2007 explaining the four pillars of nano-safety. I am a technology futurist and is currently focused on nanoelectronics, single digit nanomaterials, and 3D printing at the nanoscale. My experience includes three startups, two of which I founded, 13 years at SEMATECH, where I was a Senior Fellow of the technical staff when I left, and 12 years at General Electric with nine of them on corporate staff. I have a Ph.D. from the University of Texas at Austin, an MBA from James Madison University, and a B.S. in Physics from the Illinois Institute of Technology.

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