2D Materials are Making Progress

The recent past few months have seen a few published articles on 2D materials and their applications.  The pace is picking up.

One of the challenges of 2D materials is that the materials need to be incorporated into some other material.  A future possibility for semiconductor device transistors requires there must be a means of combining the 2D material with the silicon (or other material) substrate rapidly and in volume.   There are two significant issue with this combination.  One of the issues is that the 2D material and the semiconductor substrate require different temperatures that can damage the material already on the substrate.  The other is that the existing processes are not compatible with high-volume manufacturing.  Researchers in Sweden and Germany [Ref. 1] have developed a process that uses a standard dielectric and available wafer bonding equipment. 

The researchers attached the 2D material, which in on a wafer, and the semiconductor wafer.  Using pressure at room temperature, the two wafers are pressed together, and the temperature raised until the dielectric becomes viscous and allows the 2D material to conform to the surface of the existing material on the semiconductor wafer.  There efforts have been successfully demonstrated on a 100mm silicon wafer with uniform coverage and little strain in the 2D structures.

The development of 2D transistors has also been improving [Ref. 2], Professor Saptarschi Das of Penn State has worked on the viability of transistors from 2D materials.  The purpose of the research is to determine if the 2D transistor can be the future of semiconductors with a significantly reduced footprint.  This also implies the potential for faster speeds.  Reference 3 addresses the promises and prospects of 2D transistors.  It points out that there have been many proof-of-concept demonstrations.  There might be a need to evaluate the 2D transistors to a slightly different criteria to determine the performance of the devices.  This concept of transistor evaluation is also addressed in an Applied Physics Letters [Ref. 4], and it addresses specific parameters that need to be considered. 

Imec researchers are of the opinion that transistors made from 2D materials could become available in the near future [Ref. 5].  While they indicate that silicon will remain the primary source for the microscale electronics, transistors constructed from transition metal dichalcogenides have potential.  The challenge is creating a single atom layer that is a natural semiconductor. 

The need for the change in the transistor construction is due to the every shrinking geometry of the current transistor.  As the structure of the transistor becomes smaller and smaller, the potential for unwanted/spurious leakage of electrons continues to increase.  This is caused by the physical limits of the material property.  There have been design changes in the structure of the transistors, but the limits of material properties and the designs needed to circumvent this issue are continually getting more difficult.    A detailed discussion of the challenges of 2D materials and their application to transistor is available in Reference 6

The challenges of developing the most suitable material, creating an electronic structure that is efficient and fast, along with engineering a manufacturing process that is both high-speed and high-yield is non-trivial.  2D material transistors are coming, but it will take some time before 2D transistors are in main-stream production.  But, the 2D materials are coming.


  1. https://www.techbriefs.com/component/content/article/tb/insiders/electronics-sensors/stories/38954?
  2. https://www.techbriefs.com/component/content/article/tb/insiders/electronics-sensors/stories/38953?
  3. https://www.nature.com/articles/s41586-021-03339-z
  4. https://aip.scitation.org/doi/10.1063/5.0029712
  5. https://spectrum.ieee.org/semiconductors/materials/coming-soon-to-a-processor-near-you-atomthick-transistors
  6. https://pubs.rsc.org/en/content/articlelanding/2015/nr/c5nr01052g#!divAbstract

About Walt

I have been involved in various aspects of nanotechnology since the late 1970s. My interest in promoting nano-safety began in 2006 and produced a white paper in 2007 explaining the four pillars of nano-safety. I am a technology futurist and is currently focused on nanoelectronics, single digit nanomaterials, and 3D printing at the nanoscale. My experience includes three startups, two of which I founded, 13 years at SEMATECH, where I was a Senior Fellow of the technical staff when I left, and 12 years at General Electric with nine of them on corporate staff. I have a Ph.D. from the University of Texas at Austin, an MBA from James Madison University, and a B.S. in Physics from the Illinois Institute of Technology.

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