Is there an end to transistor area density shrinkage?

Moore’s Law is quoted in many different forms.  Basically, area density is a primary focus.  If the difference between generations in a 30% reduction in dimensions, then the area for a transistor (70% by 70%) is reduced by almost 50% (length times width).  With the first comings of the 3nm generation and the 2nm (or 20 Angstrom) generation in the planning stages, is there a limit on what can be done on a single planar surface?  The different types of transistor formations have been covered in previous blogs.  The question is what comes next.   The most promising has been two dimensional materials. 

Gate length is the dimension that the electrons travel to flow in the transistor.   The “gate” is the mechanism that permits or inhibits the flow of electrons from the source (of the electrons) to the drain.  The “gate” switches on and off in response to a controlling voltage.  Below a certain dimension, about 5nm, the silicon can not effectively control the flow of electrons. 

Aware of this limit, researchers have been working with two-dimensional material.  Molybdenum disulfide has been employed in creating, working two-dimensional transistors.  (cf. February 2022 blog)  This material is three sheets of single atom material consisting of sulfur, molybdenum, and sulfur.  Work has been done to produce transistors with gate lengths of 1nm using carbon nanotubes and molybdenum sulfide.  Chinese researchers have taken this one small step further by creating a vertical structure (Ref. 1) with a gate length of 0.34nm (3.4 Angstroms).  The structure is similar to a stair step.  The surface of the stair is a single atomic layer of molybdenum sulfide on top of an insulator of hafnium dioxide.  More details in Reference 1.  The transistor effect occurs on the vertical step, which is the single layer of atoms.

There is additional work being conducted to evaluate the impact of current switching on nano scale structures.  Work has shown that there are minor changes in the gate lengths on switching.  By increasing the gate width to almost 5nm, the devices can improve the leakage situation at very small dimensions. 

Does this work imply that the end is in sight for the continual shrinkage of circuitry.  The answer is “NO!”.  Work is being done on three-dimensional circuity where additional circuitry is stacked on top of an existing layer.  3-D structures have been explored and shown great possibility.  Improving density by adding a second level of circuitry is equivalent to a dimensional reduction to 70% of the previous dimensions.  The issue with this approach is the potential for manufacturing losses due to misalignment and the additional layers of semiconductor processing.

What is starting to emerge is the creation of “chiplets”, which are small segments of circuitry that can perform one or more functions.  By combining these chiplets with other circuitry, it is possible to create unique circuits through assembling/interconnecting chiplets with other circuitry, which in effect is 3-D semiconductors.  The advantage to this approach would be higher yields and lower overall costs.  If the chiplets are thinned, the total semiconductor thickness can be controlled.

But, the story does not end there.  The development of metamaterials can provide additional options.  Next month, metamaterials will start to be explored depth.

References:

  1. https://spectrum.ieee.org/smallest-transistor-one-carbon-atom

About Walt

I have been involved in various aspects of nanotechnology since the late 1970s. My interest in promoting nano-safety began in 2006 and produced a white paper in 2007 explaining the four pillars of nano-safety. I am a technology futurist and is currently focused on nanoelectronics, single digit nanomaterials, and 3D printing at the nanoscale. My experience includes three startups, two of which I founded, 13 years at SEMATECH, where I was a Senior Fellow of the technical staff when I left, and 12 years at General Electric with nine of them on corporate staff. I have a Ph.D. from the University of Texas at Austin, an MBA from James Madison University, and a B.S. in Physics from the Illinois Institute of Technology.

Category(s): Semiconductor Technology

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