A coming disruption in technology? Part 1

There have been many years since the 1998 announcement of carbon nanotube transistors.  The hope has been for the semiconductor industry to create a means of producing a carbon nanotube computer.  First, why is there a need to replace the current semiconductor manufacturing process?  The ability to reduce the minimum feature size dimension by 30% has been occurring on re regular basis of 18 to 24 months for decades.  A 30% reduction results in the dimension shrinking to 70% of the previous size.  With both length and width shrinking 70%, the are required is 49% of the previous area.  Consequently, twice as many features can be fabricated in the same area as previously possible. 

The imaging process (lithography) is limited by the minimum feature size possible from the source that produces the images.  Lithography tools produce images that have much greater precision than the best photographic lenses available today.  In addition to the high precision of the lithography equipment, there are a number of optical tweaks that can further refine the image quality.  There is a physical limit on how far engineering can push the physical limits of imaging.  Optical lithography went from visible wavelength to ultraviolet wavelengths (shorter wavelengths) and then to even shorter wavelengths.  The current latest lithography tools employ a wavelength of 13.5 nanometers (nm).  This is being used to produce images that have one of their dimensions under 10nm.  (If interested in further reading on the latest processes, please see reference #1.)

There are challenges as the dimensions shrink.  Multiple process steps require higher precision equipment and more costly steps.  Additional manufacturing steps increase the amount of time required to manufacture the semiconductors.  Additional steps also provided opportunities for decreasing the yields of the final devices.  All of this raises cost.

As dimensions shrink, there is potential for unwanted electrical characteristics to become present.  This degrades the performance of the devices.  As the size shrinks and more electronics circuitry is incorporated, the total distance the signals must travel in a device increases.  There are some estimates that 50% of the power for the leading edge devices is used to move the electrical signals through the circuitry. 

Why does the industry continue on as it has in the past?  Currently, there is nothing else that can produce billions of connected transistors every second.

According to a C&EN article (Ref. 2), DARPA is interested in carbon nanotube circuits.  There are a number of methods to apply the nanotubes into circuitry that will provide better performance with lower power consumption.  One of the challenges mentioned in the article is the caution needed in handling some of the exotic materials within the clean space required for semiconductor manufacturing.    Many materials can have very detrimental impacts of the production process. 

Back in the 1990s, the Advanced Technology Development Facility of SEMATECH instituted a process where they could annually handle as many as 40 different exotic and potentially process disastrous materials without danger of contamination.

The process for producing the carbon nanotubes requires a seed for growth of the tubes.  Typically, the seed material is one that should not be permitted to be the clean environment of semiconductor manufacturing.  It can be done correctly and provide the safety controls required to manufacture the semiconductors.

Part 2 will cover the possible types of transistor designs under consideration and some of the issues in implementing them into existing manufacturing.


  1. https://spectrum.ieee.org/semiconductors/nanotechnology/euv-lithography-finally-ready-for-chip-manufacturing
  2. https://cen.acs.org/materials/electronic-materials/Carbon-nanotube-computers-face-makebreak/97/i8

About Walt

I have been involved in various aspects of nanotechnology since the late 1970s. My interest in promoting nano-safety began in 2006 and produced a white paper in 2007 explaining the four pillars of nano-safety. I am a technology futurist and is currently focused on nanoelectronics, single digit nanomaterials, and 3D printing at the nanoscale. My experience includes three startups, two of which I founded, 13 years at SEMATECH, where I was a Senior Fellow of the technical staff when I left, and 12 years at General Electric with nine of them on corporate staff. I have a Ph.D. from the University of Texas at Austin, an MBA from James Madison University, and a B.S. in Physics from the Illinois Institute of Technology.

Category(s): Uncategorized

Leave a Reply