The Shrinking Dimensions

As semiconductor manufacturing continues the dimensional shrinking process, novel ideas are required to achieve the ability to continue shrinking the dimensions while increasing the performance.  There are some thoughts that this potion of the Moore’s law curve will provide some additional benefits.

As the industry moves into the sub 10 nanometer nodes, physical properties become major role players in what will be able to be manufactured in volume *with sufficient yields) and what won’t work.  Intel has released its roadmap [Ref. 1] for the smaller dimensions and is moving away from the nanometer scale.  After the 3nm node, it will not be the 2nm node. Instead, it will be the 20 Angstrom node. That will be followed by the 18 Angstrom node.  [An Angstrom is 10-9 meters or a tenth of a nanometer.  It is not a new term. Angstroms were used in optics for hundreds of years.].

While the size terminology is interesting, it is the actual physical propertied and the manufacturing of the completed devices that are the objective. 

Filed Effect Transistors [FETs], and specifically MOSFETs manage current flow by controlling current flow.  The gate electrode and the channel are two plates of a capacitor.  Unfortunately, the gate capacitance depends on the material properties at the dimensions required.  The loss of the needed parameters as size shrinks is driving the investigation to what are being called two-dimensional semiconductors. [Ref. 2] More detail on this topic is available in our April 2021 blog. [Ref. 3]

In the article with Intel’s planned roadmap, there is mention that starting at 20A, Intel is considering changing to a “gate all-around” structure [GAA].  The Intel approach is somewhat different from others working on GAA and their modification is being called the ribbonFET.  [Ref. 1]

Another topic of current interest is “chiplets”.  [Ref. 4] The concept behind this is to create individual segments for a system and be able to place them in positions that are favorable to data transfer and processing.  This approach is a means of reducing costs while achieve apparent scaling benefits.  On a larger scale there are many companies working on various approached to reduce dimensions by using multiple levels (this is not multiple layers) with interconnections to complete the system interconnections.  I know of one sensor system that has multiple levels for a complete autonomous sensor system with capabilities of working in temperatures of over 120C and over 10K PSI.  It has sensors and can store data for up to a week before being wirelessly interrogated for data transmission.  This device is under 8mm in diameter.  It will be shrunk to under 5mm in the near future but taking it to under 1,000 microns would be a challenge without moving to something like the chiplet approach.

While the topic of semiconductors is mainly about shrinking feature sizes and increasing processing capability, the real changes will come from nanomaterial characteristics.  The fact that today, researchers are developing a method to layer different 2-dimensional materials together indicates the direction.  For this to be successful, the method to develop large scale 2-D material without defects still remains a challenge.  It will happen, but will require development efforts.

References:

  1. https://www.eetimes.com/intel-charts-manufacturing-course-to-2025/#
  2. https://semiengineering.com/thinner-channels-with-2d-semiconductors/
  3. http://www.nano-blog.com/?m=202104
  4. https://semiengineering.com/piecing-together-chiplets/?cmid=291477a6-f062-4738-b59f-1ec44fd21e39

About Walt

I have been involved in various aspects of nanotechnology since the late 1970s. My interest in promoting nano-safety began in 2006 and produced a white paper in 2007 explaining the four pillars of nano-safety. I am a technology futurist and is currently focused on nanoelectronics, single digit nanomaterials, and 3D printing at the nanoscale. My experience includes three startups, two of which I founded, 13 years at SEMATECH, where I was a Senior Fellow of the technical staff when I left, and 12 years at General Electric with nine of them on corporate staff. I have a Ph.D. from the University of Texas at Austin, an MBA from James Madison University, and a B.S. in Physics from the Illinois Institute of Technology.

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