Where Wafer Scale Integration Came From

This is a story that starts in the early days of electronics.  As new concepts were developed for applications employing electricity, there was a need to develop a means of assembling components into completed electric circuits.  The “breadboard” was developed.  It was a non-conducting material with holes punched through the material in regular rows and columns.  By inserting components through the holes and soldering wires, circuit connections could be created.  Vacuum tube electronics were able to work as a means of controlling the flow of electricity through the circuit.  Obviously, this process was not viable for consumer products, which needed to be manufactured in volume.  Vacuum tube electronics date to the early 1900s and were used in sound recording and reproduction.

Printed wiring boards (PWBs) (also known as printed circuit boards (PCBs)) were developed.  Copper patterns were created on the insulating substrate (board) and holes drilled with components were to be inserted.  After the components were inserted, the PWB with components (resistors, capacitors, inductors, vacuum tube mounts, connectors, etc.) was passed through a soldering machine.  This machine had molten solder (primarily a tin-lead composition) in a large tank/bath.  A standing wave was created and the PWB passed over the standing wave just touching the component-board surface.  This created an assembly with the components firmly attached to the board.  Connectors permitted tying additional PWBs together to create the desired electrical system.

As system became more complex, the quantity of PWBs to create the desired system became very large and the number of vacuum tubes per PWB increased.  The weak link in these systems was the vacuum tubes.  Their life span was quite variable and when there were a large number of vacuum tubes involved, the system reliability was poor.  Companies that required high reliability of available functioning time, needed to find a better solution. 

Among those companies in need was AT&T.  Their Bell Labs was given the task to develop  a reliable substate.  The vacuum tube switching circuits were constantly needing to have vacuum tubes replaced.  In addition, vacuum tubes take time to “warm” up to function properly.  While the tubes are functioning, they ae generating heat.  Heat is a source of their failure.  In December 1947 (an interesting year for other reasons), Bell Labs researchers demonstrated a signal output increase when two gold contacts were applied to a germanium substrate. [Ref. 1]  The first demonstration of the transistor effect.  The development of the transistor grew rapidly.  In the late 1950s, Jack Kilby (Texas Instruments) developed a memory cell, which was a combination of various transistors on a single substrate.  Shortly after this development, Robert Noyce created a planar circuit that had the interconnections (wires) integrated into the surface of the substrate.   It was an integrated circuit (IC).

Fast forward to the early 1970s and Intel developed a 4 bit microcontroller, which was rapidly followed by 8 bit and then 16 bit microcontrollers. [Ref. 3] The advantage of the microcontroller was that it provided a means of changing the function of the circuitry without having to physically change the actual circuit.  The need for additional functions in the circuitry has led to a continual growth in complexity of the circuits.  This challenge has led to the continual development of greater and greater number of features on the IC.  In order to accomplish this, smaller and smaller features were continually developed.  (cf. Moore’s Law Ref. 4 for more details.)

The current, newer and more capable devices with billions of transistors have a limit due to the number of output connections for the devices.  These ICs, like all the previous ones, are mounted on PWBs for interconnections.  There is time required for the electrical signals from one IC to travel to the PWB interconnection, traverse the PWB circuit lines, and then enter the desired IC.  While these times are a fraction of a fraction of a second, these times delay the processing. 

A possible solution is to create the desired circuit on a single silicon wafer instead of using multiple types of ICs attached to a PWB.  This solution is called wafer scale integration.   Researchers from UCLA have proposed “packing dozens of servers’ worth of computing capability onto a dinner-plate-size wafer of silicon.” [Ref. 5] There are a number of challenges and some ideas on how to solve this need.

Next month’s blog will discuss “Chiplets”.

References:

  1. https://en.wikipedia.org/wiki/Transistor
  2. https://gildersdailyprophecy.com/posts/wafer-scale-integration-is-underway
  3. https://en.wikipedia.org/wiki/Transistor
  4. Moore’s law – Wikipedia
  5. https://spectrum.ieee.org/goodbye-motherboard-hello-siliconinterconnect-fabric#toggle-gdpr

About Walt

I have been involved in various aspects of nanotechnology since the late 1970s. My interest in promoting nano-safety began in 2006 and produced a white paper in 2007 explaining the four pillars of nano-safety. I am a technology futurist and is currently focused on nanoelectronics, single digit nanomaterials, and 3D printing at the nanoscale. My experience includes three startups, two of which I founded, 13 years at SEMATECH, where I was a Senior Fellow of the technical staff when I left, and 12 years at General Electric with nine of them on corporate staff. I have a Ph.D. from the University of Texas at Austin, an MBA from James Madison University, and a B.S. in Physics from the Illinois Institute of Technology.

Category(s): Semiconductor Technology

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