Chiplets – What are semiconductor chiplets and why needed

As there are more references to the development of semiconductor chiplets, it might be useful to consider what they are and why they are needed. As the size of the semiconductor features shrink, more and more transistors can be packed into the same area. This increase in density of features permits the continual progress following the predictions of Moore’s Law. There are consequences to this increase in density. One is that as more and more capabilities are added, there is a need to provide additional means of having the device’s functions available to the external world. This necessitates the increase in the number of input/output (i/o) connections for the device. There is a limit on how dense the spacing of these i/o points are due to the need to be able an connect to each and every point to additional circuitry without misconnecting the device.

The solution to the issue of handling the interconnects has seen a number of answers. Incorporating newer (custom designed?) materials and developing customized techniques including 2.5D, 3D-IC, wafer level packaging, and system-in-package [cf. Ref. 1 for additional details] are among the possibilities. There are among the new ideas for developing interconnects and other possibilities to output signals and information.

The larger influencing factor is the cost to implement and manufacture. According to Reference 2: “There are fewer customers at 5nm than there were at 7nm, and there were fewer at 7nm than at 10nm, because a smaller number of companies can extract value from the large capital investments needed to develop these new products.” The issue is funding. Any design needs to be able to provide a return on the development and production costs. The author has heard of the design costs for a leading-edge device to be as high as $100M or more! That also indicates the hours to develop all aspects of the design, including the tooling needed for manufacturing. What is an acceptable defect rate for 100 million transistors on a single device becomes a disaster then there are 10 of billions of transistors on the device.

A solution is needed. Enter the concept of the “chiplet”. As Reference 3 explains, a chiplet is a sub-device item that provides certain predetermined functions. One example is that the chiplet could be the fully operational specialized timing circuit. If this concept moves forward, and it appears to be doing so, there will be libraries of function designs that can be selected from to perform specific actions/calculations. These chiplets can be packaged and mounted, directly mounted to the wafer (similar to flip chip assembly on the printed wiring board level), or wafer segment to wafer level bonding. The effort to create these new capabilities will not be easy. Several major manufacturers have created a consortium [Ref. 4] to standardize the specifications and capabilities of chiplets.

The question is why are these needed. Reference 5 describes the need to faster computing power. The latest exascale super computer CPU and GPU designs mix and match complex chip functions in advanced packages. These computers will be 1,000 faster than the existing super computers. “That’s beginning to change. Some, but not all, exascale supercomputers are using a chiplet approach, particularly the U.S.-based systems. Instead of an SoC, the CPUs and GPUs in these systems incorporate smaller dies or tiles, which are then fabricated and reaggregated into advanced packages. Simply put, it’s relatively easier to fabricate smaller dies with higher yields than large SoCs.”

On the smaller scale, the chiplets can provide time-saving designs that can produce devices in very small packages. The medical community benefits from smaller devices, especially in implanted devices. Typically, smaller devices will require less power, which in turn provides a longer battery life. In other cases, the ability to reduce the size of the device enable applications that are not currently possible. Will everything go to chiplets, probably not. Advanced capability devices can benefit from more efficient packaging, which chiplets appear to provide. The future will inform us of how effective chiplets can be.


About Walt

I have been involved in various aspects of nanotechnology since the late 1970s. My interest in promoting nano-safety began in 2006 and produced a white paper in 2007 explaining the four pillars of nano-safety. I am a technology futurist and is currently focused on nanoelectronics, single digit nanomaterials, and 3D printing at the nanoscale. My experience includes three startups, two of which I founded, 13 years at SEMATECH, where I was a Senior Fellow of the technical staff when I left, and 12 years at General Electric with nine of them on corporate staff. I have a Ph.D. from the University of Texas at Austin, an MBA from James Madison University, and a B.S. in Physics from the Illinois Institute of Technology.
Semiconductor Technology

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