There has been a lot written about 2-D transistors and the coming applications involving the properties of the circuitry and its ability to create denser circuitry. There are challenges as the circuit density increases. While very small, the distance that an electrical signal needs to travel reduces the effective speed of the processor. So, one solution is to place small pieces of memory near the processor circuitry. It is also possible to place small amounts of specialized circuitry near other resources required by that circuitry.
Let’s consider the issues as stand-alone problems, which they are not. If one considers chiplets, there is the problem of aligning the chiplet with the circuitry that it is being attached to. Since the line widths are on the order of low digit nanometers alignment is critical. The methodology for blind alignment would require high precision on the dimensions of the chiplet. One solution would be to thin the wafer so that the circuitry being mounted is transparent and can be accurately aligned. While this may seem unreasonable, thinning wafers to below 30 µm changes the transmission of light through the wafer so that alignment can be done with a great deal of accuracy. Next, let’s consider attachment. Since the circuitry is being miniaturized the available space for bonding pads becomes much smaller. So, the question that comes up is how much is the minimum amount of area that is required to guarantee a connection which does not change under temperature loading. Work is being done in this area, but there is no agreed upon direction at this time. Even when these problems are sufficiently solved to permit manufacturing, the question comes up how to inspect the joints/connections of the two pieces of circuitry. Visual inspection is highly improbable since even thinned wafers would have circuit minds on the substrate that blocked the ability to visually inspect. Solving this problem then raises another question. The current design of semiconductors is such that the bottom of the semiconductors can be mounted tightly to a heat transfer material. This permits the ability to cool the devices that are generating heat and take that heat away from the circuit. High temperatures over long periods of time tend to degrade the performance of the circuitry. If one considers the stacked circuits, the upper portions of the stack circuit do not have the thermal conductivity that would exist if it were a single level of circuitry. That raises the question of what is the heat contribution to these upper-level devices and will it cause early failure. This needs to be addressed, and people are working on it. However, we don’t have the solution in hand yet. So, 3-D circuitry has potential but there are many issues that need to be addressed.
One area that 3-D had provided some promise is the attempt to print batteries onto circuits. Back in 2016, there were proposals to employ a 3-D holographic lithography to create these batteries [Ref. 1]. The limiting factor is the 3-D creation of thee required electrode formation. There are current claims regarding the development of 3-D printed batteries [Ref. 2], but the public release has been slow.
3-D electronics has potential to improve the existing products, but there is still much research and development required.
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